Rewrite of a nonvolatile memory such as an EEPROM is performed by applying a high voltage to a memory cell. Thus, the nonvolatile memory includes a boosting circuit for supplying a required high voltage to the memory cell. Moreover, in order to monitor a boosting potential of the boosting circuit and to evaluate a write margin of the memory cell in wafer inspection before dicing, an output line of the boosting circuit is often connected to a test pad.
This test pad is not used after the wafer inspection. Thus, in case that the nonvolatile memory is mounted on an integrated circuit card (IC card) having strict security restrictions and the like, the test pad is arranged on a dicing line and cut off along with dicing.
However, if the test pad is arranged on the dicing line, a metal wiring connected to the test pad may be short-circuited to ground potential by dicing. Thus, there is a possibility that the output line of the boosting circuit is grounded. When the output line of the boosting circuit is grounded, a leak current is caused. Thus, a possible lowering of a boosting voltage of the boosting circuit may result.
Based on the background as described above, a semiconductor device capable of removing the test pad without lowering the boosting voltage of the boosting circuit has been proposed. This conventional semiconductor device is described in Japanese Patent Publication (Kokai) No. 2000-40792.
With reference to FIG. 7, description will be given of the conventional semiconductor device described above. FIG. 7 is a block diagram showing a structure of the conventional semiconductor device in its wafer state.
In a chip region 202 sectioned by a dicing line 201, a boosting circuit 203 and a fuse 204 are provided. An output line OL of the boosting circuit 203 is connected to a memory cell. Moreover, in order to monitor a boosting potential and evaluate a write margin of the memory cell in wafer inspection before dicing, the output line OL of the boosting circuit 203 is connected to a test pad 205, which is arranged on the dicing line 201, via the fuse 204.
When the test pad is no longer in use after the boosting potential is monitored and the write margin of the memory cell is evaluated, the fuse 204 is cut off by use of a laser and the like. By cutting off the fuse 204, the output line OL of the boosting circuit 203, which is connected to the test pad 205, is electrically isolated from the test pad 205. Thus, even if the output line OL of the boosting circuit 203 is grounded by dicing, lowering of the boosting voltage of the boosting circuit 203 can be prevented.
However, in the conventional semiconductor device, since the fuse 204 is cut off by use of the laser and the like, it is required to expose the fuse 204 in forming a protective film. Thus, in a spot where the fuse 204 is provided, the output line OL of the boosting circuit 203 is exposed to the surface. From the viewpoint of security, it is desirable that the output line OL of the boosting circuit 203 is not exposed to the surface.
Moreover, in the conventional semiconductor device, in order to electrically isolate the output line OL of the boosting circuit 203 and the test pad 205 from each other, it has been required to cut off the fuse 204 by use of the laser and the like. Thus, a conventional method for testing a semiconductor device has had to include the following steps. Specifically, after the boosting potential is monitored and the write margin of the memory cell is evaluated by a tester, a wafer is transferred to a fuse blow device to cut off the fuse 204. Thereafter, the wafer is transferred again to the tester and it is inspected whether or not the output line OL of the boosting circuit 203 is in its open state. As described above, by use of the conventional method for testing a semiconductor device, the steps in the wafer inspection become complicated. Thus, cost increase in testing has been a problem.